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PIC32MX3XX/4XX
TABLE 3-2:
COPROCESSOR 0 REGISTERS (CONTINUED)
Register Register
Number Name
Function
17-22
23
24
25-29
30
31
Reserved
Debug (2)
DEPC (2)
Reserved
ErrorEPC (1)
DESAVE (2)
Reserved in the PIC32MX3XX/4XX Family core
Debug control and exception status
Program counter at last debug exception
Reserved in the PIC32MX3XX/4XX Family core
Program counter at last error
Debug handler scratchpad register
Note 1:
2:
Registers used in exception processing.
Registers used during debug.
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
shows the exception types in order of priority.
TABLE 3-3:
Exception
Reset
DSS
DINT
NMI
Interrupt
DIB
AdEL
IBE
DBp
Sys
Bp
RI
CpU
CEU
Ov
Tr
DDBL/DDBS
AdEL
AdES
DBE
DDBL
DS61143G-page 38
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES
Description
Assertion MCLR or a Power-on Reset (POR)
EJTAG Debug Single Step
EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the
EjtagBrk bit in the ECR register
Assertion of NMI signal
Assertion of unmasked hardware or software interrupt signal
EJTAG debug hardware instruction break matched
Fetch address alignment error
Fetch reference to protected address
Instruction fetch bus error
EJTAG Breakpoint (execution of SDBBP instruction)
Execution of SYSCALL instruction
Execution of BREAK instruction
Execution of a Reserved Instruction
Execution of a coprocessor instruction for a coprocessor that is not enabled
Execution of a CorExtend instruction when CorExtend is not enabled
Execution of an arithmetic instruction that overflowed
Execution of a trap (when trap condition is true)
EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)
Load address alignment error
Load reference to protected address
Store address alignment error
Store to protected address
Load or store bus error
EJTAG data hardware breakpoint matched in load data compare
? 2010 Microchip Technology Inc.
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